This invention relates generally to electronic circuitry and more particularly a power-off state storage apparatus and method.
Personal electronics devices are becoming increasingly popular in today""s society. Examples electronic devices include computers, cellular phones, personal digital assistants, and calculators. Many people find it desirable to utilize these types of electronic devices in a mobile fashion, remote from a fixed electrical supply. Therefore, many electrical devices utilize batteries for their power supply.
Important to a battery-powered device""s marketability is its battery life. Therefore manufacturers take steps to increase battery life by reducing power consumption. One way of reducing power consumption of a powered battery-powered device is to terminate power to components of the device when those components do not require power. For example, a microprocessor embedded in a wireless phone that controls the phone keypad may be shut down and restarted once every millisecond to save power. The problem that this creates is uncertainty in the state of the microprocessor when power was terminated. In other words, it important to know what values were stored in certain registers, but this is difficult if power is terminated to those registers.
One way manufacturers have addressed this problem is to provide persistent memory that retains its stored values for a long period of time after power is terminated to the memory. Examples of persistent memory include flash and ferromagnetic memory. However, these types of memory require additional fabrication steps and significantly increase the cost of the associated electronic device.
Accordingly a need has arisen for a power-off state storage apparatus and method. The present invention provides a method and apparatus that addresses shortcomings of prior systems and methods.
According to one embodiment of the invention, a circuit for power-off state storage in an electronic device having a positive power supply includes a storage circuit comprising first and second storage capacitors and a write circuit having a plurality of N-type transistors coupled to the storage circuit. The write circuit is operable to write a data bit to the first and second storage capacitors. The power-off state storage circuit also has a sense amplifier connected to the storage circuit and that is operable to read the data bit stored by the storage capacitors. The first and second capacitors in the storage circuit are electrically isolated from the positive power supply such that when the positive power supply is terminated any charge stored on the first and second capacitors is prevented from discharging to the terminated power supply.
According to another embodiment of the invention, a method for storing data while power is terminated to an electronic device includes providing power to the device and providing a storage circuit having at least one storage capacitor electrically isolated from any power in the device such that, when power to the device is terminated, any data stored in the at least one storage capacitor is retained for at least a predetermined time period. The method also includes writing a data bit to the at least one storage capacitor, terminating power to the device and, within the predetermined time period, providing power to the device again, and then sensing the stored data.
Some embodiments of the invention provided numerous technical advantages. For example, some embodiments of the invention allow storage of data when power is terminated to the associated portion of an electronic device. By storing data while power is terminated, battery life may be increased by more frequent termination when certain portions of an electronic device are not used. Furthermore, such advantages may be obtained without the cost of persistent memory, such as flash and ferromagnetic memory.
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.